In a typical digital communication system, a receiver samples a transmitted analog signal using a predetermined sampling clock to convert the sampled analog signal to a digital signal. Some systems synchronize the received signal to the transmitted signal by including timing and phase information within the data stream, which the receiver uses directly. More sophisticated digital processing enables the receiver to determine phase and timing from characteristics of the received data stream itself, when the transmitter does not explicitly include separate time and phase information in a transmission. This technique is referred to as timing and phase recovery, which saves bandwidth by eliminating the recurring need to transmit timing and phase data.
FIG. 1 is a block diagram showing a prior art digital timing recovery circuit, wherein timing recovery is realized through a feedback loop. The digital timing recovery circuit comprises a sampling clock generator 11, a first sampler 12, an interpolator 13, a data filter 14, a timing error detector 15, a loop filter 16, and a controller 17. The sampling clock generator 11 controls the time period Ts at which discrete samples are taken, in which aliasing does not occur. The first sampler 12 generates and outputs a signal X(mTs), which samples a band limited input signal X(t) according to the sampling clock 11. The interpolator 13 generates and outputs an interpolant y(kTi) at a time Ti between samples taken by the first sampler 12 at times Ts. The data filter 14 filters the interpolant y(kTi) to output the final data strobe. The timing error detector 15 detects a timing error from the data strobe. The loop filter 16 removes a noise component of the detected timing error. The controller 17 controls operation of the interpolator 13 by using the filtered timing error to perform the exact timing recovery.
However, the circuit shown in FIG. 1 is limited to a scalar (single channel) input and is not appropriate for a vector (multi-channel) input. Multi-channel applications are becoming increasingly important as researchers refine techniques for multiple-input, multiple-output (MIMO) systems wherein a transmitter and/or receiver employ multiple antennas. MIMO systems are of increasing interest, especially for wireless applications, for their potential to provide greatly increased data rates over a set bandwidth as compared to single channel systems.
Another disadvantage of the circuit of FIG. 1 is that the interpolator 13 interpolates or resamples once rather than resampling and reinterpolating the data multiple times within each period Ts. As such, the prior art circuit of FIG. 1 is limited to operation with a baseband signal input X(t) and cannot process a passband signal input.